A mixed-monotonic capacitor switching scheme which can provide stable common-mode voltage (Vcm) without any additional voltage regulator and compensation capacitor array is proposed for the successive approximation register (SAR) analog-to-digital (ADC). The proposed scheme contains two equal amplitude but opposite monotonicity switched capacitor arrays, the stabilization of the common mode voltage is achieved with self-complementation of the differential voltage. Based on this technique, a 10-bit 50 MS/s prototype is designed in CMOS 0.18 μm technology. A window opening SAR logic is used to reduce the transmission time from the comparator out to DAC control signal. An adaptive delay chain is used in the comparator loop to reduce the conversion time of lower bit in the SAR ADC. Measurement result shows that the SAR ADC can achieve a SNDR equal to 57.31 dB, and INL and DNL are equal to 1.81 LSB and 0.98 LSB respectively.

The authors propose a top-down design process for MASH21 modulator. In system level, coefficient scaling is used to limit integrator’s output; in circuit level, integrator transient modeling is used to analyze the effect caused by OP’s non-ideality, and get the optimized design region for SNR, area and power. A MASH21 modulator for digital audio application is designed to verify the proposed design criteria. This experimental prototype is implemented with TSMC18MMRF, operates under a single 1.8 V power supply, and achieves a measured SNDR of 91dB.

An ultra-low power passive UHF RFID transponder complying with ISO/IEC 18000-6B protocol is presented. In order to provide an accurate clock for the digital baseband processing, an ultra-low power and self-calibrated clock generator is designed and implemented in the transponder with a clock variation within 4% against temperature from -50℃ to 120 ℃ or supply voltage from 0.7 to 1.6 V. Total power consumption of the novel clock generator is only 364 nW with 0.7V supply voltage. Further, a low voltage bandgap reference which generates 0.96 V with 100 nA current consumption is introduced. In digital baseband, clock gating and module reuse strategies are employed to further reduce the power consumption to 1.17 μW. This design is fabricated in 0.18 μm mix-signal CMOS process with a die size of 0.75 mm×0.75 mm. Measurement results show that the proposed RFID transponder operates with a sensitivity of -10 dBm.

A digital baseband receiver which supports both ISO 18000-6B and 6Cfor UHF RFIDradio frequency identification reader is described. The digital baseband receiver includes deci mation filters, dc-removed filters, phase-recovery module, and so on. A novel decoder in digital baseband is also proposed. An approach to compensate the effect of zero-point excursion based on the zero-detect method is presented in the decoder. Simulation and verification results indicate that the new approach needs less hardware resources and less time to decodethe signal, compared with the correlation based demodulation method. Total chip area without test pads is 730 μm ×3375 μm @0. 18 μm CMOSprocess and consumes 32. 89 mW, whilethe decoder occupies the 1% of total area and consumes 0. 23mW.